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general description the max5580?ax5585 quad, 12-/10-/8-bit, voltage- output, digital-to-analog converters (dacs) offer buffered outputs and a 3s maximum settling time at the 12-bit level. the dacs operate from a +2.7v to +5.25v analog supply and a separate +1.8v to +5.25v digital supply. the 20mhz, 3-wire, serial interface is compati- ble with spi, qspi, microwire, and digital sig- nal processor (dsp) protocol applications. multiple devices can share a common serial interface in direct- access or daisy-chained configuration. the max5580 max5585 provide two multifunctional, user-programma- ble, digital i/o ports. the externally selectable power-up states of the dac outputs are either zero scale, mid- scale, or full scale. software-selectable fast and slow settling modes decrease settling time in fast mode, or reduce supply current in slow mode. the max5580/max5581 are 12-bit dacs, the max5582/max5583 are 10-bit dacs, and the max5584/max5585 are 8-bit dacs. the max5580/ max5582/max5584 provide unity-gain-configured out- put buffers, while the max5581/max5583/max5585 provide force-sense-configured output buffers. the max5580?ax5585 operate over the extended -40? to +85? temperature range and are available in space-saving, 5mm x 5mm x 0.8mm, 20-pin, thin qfn and tssop packages. applications portable instrumentation automatic test equipment (ate) digital offset and gain adjustment automatic tuning programmable voltage and current sources programmable attenuators industrial process controls motion control microprocessor (?)-controlled systems power amplifier control fast parallel-dac to serial-dac upgrades features ? 3s (max) 12-bit settling time to 0.5 lsb ? quad, 12-/10-/8-bit serial dacs in tssop and thin qfn (5mm x 5mm x 0.8mm) packages ? 1 lsb (max) inl and dnl at 12-bit resolution ? two user-programmable digital i/o ports ? single +2.7v to +5.25v analog supply ? +1.8v to av dd digital supply ? 20mhz, 3-wire, spi-/qspi-/microwire-/dsp- compatible serial interface ? glitch-free outputs power up to zero scale, midscale, or full scale controlled by pu pin ? unity-gain or force-sense-configured output buffers max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ________________________________________________________________ maxim integrated products 1 19-3164; rev 1; 5/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations appear at end of data sheet. ordering information continued at end of data sheet. evaluation kit available spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. selector guide part output buffer configuration resolution (bits) inl ( lsb max) max5580aeup unity gain 12 ? MAX5580AETP unity gain 12 ? max5580beup unity gain 12 ? max5580betp unity gain 12 ? max5581aeup force sense 12 ? max5581aetp force sense 12 ? max5581beup force sense 12 ? max5581betp force sense 12 ? max5582eup unity gain 10 ? max5582etp unity gain 10 ? max5583eup force sense 10 ? max5583etp force sense 10 ? max5584eup unity gain 8 ?.5 max5584etp unity gain 8 ?.5 max5585eup force sense 8 ?.5 max5585etp force sense 8 ?.5 part temp range pin-package max5580 aeup* -40? to +85? 20 tssop-ep** MAX5580AETP* -40? to +85? 20 thin qfn-ep** ordering information * future product?ontact factory for availability. specifications are preliminary. ** ep = exposed paddle.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = 2.7v to 5.25v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v (for av dd = 2.7v to 5.25v), v ref = 4.096v (for av dd = 4.5v to 5.25v), r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to dv dd ........................................................................?v agnd to dgnd ..................................................................?.3v av dd to agnd, dgnd.............................................-0.3v to +6v dv dd to agnd, dgnd ............................................-0.3v to +6v fb_, out_, ref to agnd ........-0.3v to the lower of (av dd + 0.3v) or +6v sclk, din, cs , pu, dsp to dgnd .......-0.3v to the lower of (dv dd + 0.3v) or +6v upio1, upio2 to dgnd ...............-0.3v to the lower of (dv dd + 0.3v) or +6v maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70 c) 20-pin tssop (derate 21.7mw/ c above +70 c) ........1739mw 20-pin thin qfn (derate 20.8mw/ c above +70 c) ....1667mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units static accuracy max5580/max5581 12 max5582/max5583 10 resolution n max5584/max5585 8 bits max5580a/max5581a (12 bit) ? max5580b/max5581b (12 bit) ? ? max5582/max5583 (10 bit) ?.5 ? integral nonlinearity inl v ref = 2.5v at av dd = 2.7v and v ref = 4.096v at av dd = 5.25v (note 2) max5584/max5585 (8 bit) ?.125 ?.5 lsb differential nonlinearity dnl guaranteed monotonic (note 2) ? lsb m ax 5580a/m ax 5581a ( 12 b i t) , d eci m al cod e = 40 5 m ax 5580b/m ax 5581b ( 12 b i t) , d eci m al cod e = 40 5 ?5 max5582/max5583 (10 bit), decimal code = 20 ? ?5 offset error v os max5584/max5585 (8 bit), decimal code = 5 5 ?5 mv offset-error drift 5 ppm of fs/ c max5580a/max5581a (12 bit) ? max5580b/max5580b (12 bit) ?0 ?0 max5582/max5583 (10 bit) ? ?0 gain error ge full-scale output max5584/max5585 (8 bit) ? ? lsb gain-error drift 1 ppm of fs/ c
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = 2.7v to 5.25v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v (for av dd = 2.7v to 5.25v), v ref = 4.096v (for av dd = 4.5v to 5.25v), r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units power-supply rejection ratio psrr full-scale output, av dd = 2.7v to 5.25v 200 ?/v reference input reference-input range v ref 0.25 av dd v reference-input resistance r ref normal operation (no code dependence) 145 200 k ? reference leakage current shutdown mode 0.5 1 a dac output characteristics unity gain 85 slow mode, full scale force sense 67 unity gain 140 output-voltage noise fast mode, full scale force sense 110 ? rms unity-gain output 0 av dd output-voltage range (note 3) force-sense output 0 av dd / 2 v dc output impedance 38 ? av dd = 5v, out_ to agnd, full scale, fast mode 57 short-circuit current av dd = 3v, out_ to agnd, full scale, fast mode 45 ma power-up time from dv dd , applied until interface is functional 30 60 ? wake-up time coming out of shutdown, outputs settled 40 ? output out_ and fb_ open-circuit leakage current programmed in shutdown mode, force-sense outputs only 0.01 ? digital outputs (upio_) output high voltage v oh i source = 0.5ma dv dd - 0.5 v output low voltage v ol i sink = 2ma 0.4 v digital inputs (sclk, cs , din, dsp , upio_) dv dd 2.7v 2.4 input high voltage v ih dv dd < 2.7v 0.7 x dv dd v dv dd > 3.6v 0.8 2.7v dv dd 3.6v 0.6 input low voltage v il dv dd < 2.7v 0.2 v input leakage current i in ?.1 ? ? input capacitance c in 10 pf
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = 2.7v to 5.25v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v (for av dd = 2.7v to 5.25v), v ref = 4.096v (for av dd = 4.5v to 5.25v), r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units pu input input high voltage v ih-pu dv dd - 200mv v input low voltage v il-pu 200 mv input leakage current i in-pu pu still considered floating when connected to a tri-state bus ?00 na dynamic performance fast mode 3.6 voltage-output slew rate sr slow mode 1.6 v/? m ax 5580/m ax 5581 fr om cod e 322 to cod e 4095 to 0.5 ls b 23 m ax 5 582/m ax 5 583 fr om cod e 10 to cod e 1023 to 0.5 ls b 1.5 3 fast mode max5584/max5585 fr om cod e 3 to code 255 to 0.5 ls b 12 m ax 5580/m ax 5581 fr om cod e 322 to cod e 4095 to 0.5 ls b 36 max5582/max5583 fr om cod e 10 to code 1023 0.5 ls b 2.5 6 voltage-output settling time (note 4), figure 5 t s slow mode max5584/max5585 fr om cod e 3 to code 255 to 0.5 ls b 24 ? fb_ input voltage 0 v ref / 2 v fb_ input current 0.1 ? unity gain 200 reference -3db bandwidth (note 5) force sense 150 khz digital feedthrough cs = dv dd , code = zero scale, any digital input from 0 to dv dd and dv dd to 0, f = 100khz 0.1 nv-s digital-to-analog glitch impulse major carry transition 2 nv-s dac-to-dac crosstalk (note 6) 15 nv-s
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = 2.7v to 5.25v, dv dd = 1.8v to av dd , agnd = 0, dgnd = 0, v ref = 2.5v (for av dd = 2.7v to 5.25v), v ref = 4.096v (for av dd = 4.5v to 5.25v), r l = 10k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units power requirements analog supply voltage range av dd 2.70 5.25 v digital supply voltage range dv dd 1.8 av dd v unity gain 0.9 1.6 slow mode, all digital inputs at dgnd or dv dd , no load, v ref = 4.096v force sense 1.6 2.4 unity gain 1.6 4 operating supply current i avdd + i dvdd fast mode, all digital inputs at dgnd or dv dd , no load, v ref = 4.096v force sense 2.3 4 ma shutdown supply current i av d d ( s h d n ) + i d v d d ( s h d n ) no clocks, all digital inputs at dgnd or dv dd , all dacs in shutdown mode 0.5 1 a note 1: for the force-sense versions, fb_ is connected to its respective out_, and v out (max) = v ref / 2, unless otherwise noted. note 2: linearity guaranteed from decimal code 40 to code 4095 for the max5580b/max5581b (12 bit, b grade), code 20 to code 1023 for the max5582/max5583 (10 bit), and code 5 to code 255 for the max5584/max5585 (8 bit). note 3: represents the functional range. the linearity is guaranteed at v ref = 2.5v (for av dd from 2.7v to 5.25v), and v ref = 4.096v (for av dd = 4.5v to 5.25v). see the typical operating characteristics section for linearity at other voltages. note 4: guaranteed by design. note 5: the reference -3db bandwidth is measured with a 0.1v p-p sine wave on v ref and with full-scale input code. note 6: dc crosstalk is measured as follows: outputs of daca?acd are set to full scale and the output of dacd is measured. while keeping dacd unchanged, the outputs of daca?acc are transitioned to zero scale and the ? v out of dacd is measured.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 6 _______________________________________________________________________________________ timing characteristics?dsp mode disabled (3v, 3.3v, 5v logic) (figure 1) (dv dd = 2.7v to 5.25v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 2.7v < dv dd < 5.25v 20 mhz sclk pulse-width high t ch (note 7) 20 ns sclk pulse-width low t cl (note 7) 20 ns cs fall to sclk rise setup time t css 10 ns sclk rise to cs rise hold time t csh 5ns sclk rise to cs fall setup time t cs0 10 ns din to sclk rise setup time t ds 12 ns din to sclk rise hold time t dh 5ns sclk rise to doutdc1 valid propagation delay t do1 c l = 20pf, upio_ = doutdc1 mode 30 ns sclk fall to dout_ valid propagation delay t do2 c l = 20pf, upio_ = doutdc0 or doutrb mode 30 ns cs rise to sclk rise hold time t cs1 microwire and spi modes 0 and 3 10 ns cs pulse-width high t csw 45 ns upio_ timing characteristics dout tri-state time when exiting doutdc0, doutdc1, and upio modes t doz c l = 20pf, from end of write cycle to upio_ in high impedance 100 ns doutrb tri-state time from cs rise t drbz c l = 20pf, from rising edge of cs to upio_ in high impedance 20 ns doutrb tri-state enable time from 8th sclk rise t zen c l = 20pf, from 8th rising edge of sclk to upio_ driven out of tri-state 20 ns ldac pulse-width low t ldl figure 5 20 ns ldac effective delay t lds figure 6 100 ns clr , mid , set pulse-width low t cms figure 5 20 ns gpo output settling time t gp figure 6 100 ns gpo output high-impedance time t gpz 100 ns
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs _______________________________________________________________________________________ 7 timing characteristics?dsp mode disabled (1.8v logic) (figure 1) (dv dd = 1.8v to 2.7v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 1.8v < dv dd < 2.7v 10 mhz sclk pulse-width high t ch (note 7) 40 ns sclk pulse-width low t cl (note 7) 40 ns cs fall to sclk rise setup time t css 20 ns sclk rise to cs rise hold time t csh 5ns sclk rise to cs fall setup time t cs0 10 ns din to sclk rise setup time t ds 20 ns din to sclk rise hold time t dh 5ns sclk rise to doutdc1 valid propagation delay t do1 c l = 20pf, upio_ = doutdc1 mode 60 ns sclk fall to dout_ valid propagation delay t do2 c l = 20pf, upio_ = doutdc0 or doutrb mode 60 ns cs rise to sclk rise hold time t cs1 microwire and spi modes 0 and 3 20 ns cs pulse-width high t csw 90 ns upio_ timing characteristics dout tri-state time when exiting doutdc0, doutdc1, and upio modes t doz c l = 20pf, from end of write cycle to upio_ in high impedance 200 ns doutrb tri-state time from cs rise t drbz c l = 20pf, from rising edge of cs to upio_ in high impedance 40 ns doutrb tri-state enable time from 8th sclk rise t zen c l = 20pf, from 8th rising edge of sclk to upio_ driven out of tri-state 40 ns ldac pulse-width low t ldl figure 5 40 ns ldac effective delay t lds figure 6 200 ns clr , mid , set pulse-width low t cms figure 5 40 ns gpo output settling time t gp figure 6 200 ns gpo output high-impedance time t gpz 200 ns
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 8 _______________________________________________________________________________________ timing characteristics?dsp mode enabled (3v, 3.3v, 5v logic) (figure 2) (dv dd = 2.7v to 5.25v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 2.7v < dv dd < 5.25v 20 mhz sclk pulse-width high t ch (note 7) 20 ns sclk pulse-width low t cl (note 7) 20 ns cs fall to sclk fall setup time t css 10 ns dsp fall to sclk fall setup time t dss 10 ns sclk fall to cs rise hold time t csh 5ns sclk fall to cs fall delay t cs0 10 ns sclk fall to dsp fall delay t ds0 10 ns din to sclk fall setup time t ds 12 ns din to sclk fall hold time t dh 5ns sclk rise to dout_ valid propagation delay t do1 c l = 20pf, upio_ = doutdc1 or doutrb mode 30 ns sclk fall to dout_ valid propagation delay t do2 c l = 20pf, upio_ = doutdc0 mode 30 ns cs rise to sclk fall hold time t cs1 microwire and spi modes 0 and 3 10 ns cs pulse-width high t csw 45 ns dsp pulse-width high t dsw 20 ns dsp pulse-width low t dspwl (note 8) 20 ns upio_ timing characteristics dout tri-state time when exiting doutdc0, doutdc1, and upio modes t doz c l = 20pf, from end of write cycle to upio_ in high impedance 100 ns doutrb tri-state time from cs rise t drbz c l = 20pf, from rising edge of cs to upio_ in high impedance 20 ns doutrb tri-state enable time from 8th sclk fall t zen c l = 20pf, from 8th falling edge of sclk to upio_ driven out of tri-state 20 ns ldac pulse-width low t ldl figure 5 20 ns ldac effective delay t lds figure 6 100 ns clr , mid , set pulse-width low t cms figure 5 20 ns gpo output settling time t gp figure 6 100 ns gpo output high-impedance time t gpz 100 ns
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs _______________________________________________________________________________________ 9 timing characteristics?dsp mode enabled (1.8v logic) (figure 2) (dv dd = 1.8v to 2.7v, agnd = dgnd = 0, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units sclk frequency f sclk 1.8v < dv dd < 2.7v 10 mhz sclk pulse-width high t ch (note 7) 40 ns sclk pulse-width low t cl (note 7) 40 ns cs fall to sclk fall setup time t css 20 ns dsp fall to sclk fall setup time t dss 20 ns sclk fall to cs rise hold time t csh 5ns sclk fall to cs fall delay t cs0 10 ns sclk fall to dsp fall delay t ds0 15 ns din to sclk fall setup time t ds 20 ns din to sclk fall hold time t dh 5ns sclk rise to dout_ valid propagation delay t do1 c l = 20pf, upio_ = doutdc1 or doutrb mode 60 ns sclk fall to dout_ valid propagation delay t do2 c l = 20pf, upio_ = doutdc0 mode 60 ns cs rise to sclk fall hold time t cs1 microwire and spi modes 0 and 3 20 ns cs pulse-width high t csw 90 ns dsp pulse-width high t dsw 40 ns dsp pulse-width low t dspwl (note 8) 40 ns upio_ timing characteristics dout tri-state time when exiting doutdc0, doutdc1, and upio modes t doz c l = 20pf, from end of write cycle to upio_ in high impedance 200 ns doutrb tri-state time from cs rise t drbz c l = 20pf, from rising edge of cs to upio_ in high impedance 40 ns doutrb tri-state enable time from 8th sclk fall t zen c l = 20pf, from 8th falling edge of sclk to upio_ driven out of tri-state 40 ns ldac pulse-width low t ldl figure 5 40 ns ldac effective delay t lds figure 6 200 ns clr , mid , set pulse-width low t cms figure 5 40 ns gpo output settling time t gp figure 6 200 ns gpo output high-impedance time t gpz 200 ns note 7: in some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol- lowing edge. in the case of a 0.5 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7v) or 50ns (1.8v). note 8: the falling edge of dsp starts a dsp-type bus cycle, provided that cs is also active low to select the device. dsp active low and cs active low must overlap by a minimum of 10ns (2.7v) or 20ns (1.8v). cs can be permanently low in this mode of operation.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 10 ______________________________________________________________________________________ 4 2 3 0 -1 -3 1 -2 -4 0 1024 2048 3072 4095 integral nonlinearity vs. digital input code (12 bit) max5580-85 toc01 digital input code inl (lsb) b grade 1.00 0.50 0.75 0 -0.25 -0.75 0.25 -0.50 -1.00 0 256 512 768 1023 integral nonlinearity vs. digital input code (10 bit) max5580-85 toc02 digital input code inl (lsb) 0.50 0.25 0 -0.25 -0.50 064 128 192 255 integral nonlinearity vs. digital input code (8 bit) max5580-85 toc03 digital input code inl (lsb) 0.50 0.25 0 -0.25 -0.50 0 1024 2048 3072 4095 differential nonlinearity vs. digital input code (12 bit) max5580-85 toc04 digital input code dnl (lsb) b grade 0.2 0.1 0 -0.1 -0.2 0 256 512 768 1023 differential nonlinearity vs. digital input code (10 bit) max5580-85 toc05 digital input code dnl (lsb) 0.050 0.025 0 -0.025 -0.050 064 128 192 255 differential nonlinearity vs. digital input code (8 bit) max5580-85 toc06 digital input code dnl (lsb) 4 2 3 0 -1 -3 1 -2 -4 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 integral nonlinearity vs. reference voltage (12 bit) max5580-85 toc07 v ref (v) inl (lsb) b grade midscale differential nonlinearity vs. reference voltage (12 bit) max5580-85 toc08 v ref (v) dnl (lsb) 4.5 4.0 3.0 3.5 2.0 2.5 1.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 1.0 5.0 b grade midscale 4 2 3 0 -1 -3 1 -2 -4 -40 10 -15 35 60 85 integral nonlinearity vs. temperature (12 bit) max5580-85 toc09 temperature ( c) inl (lsb) b grade midscale t ypical operating characteristics (av dd = dv dd = 5v, v ref = 4.096v, r l = 10k ? , c l = 100pf, speed mode = fast, pu = floating, t a = +25 c, unless otherwise noted.)
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 11 0.2 0.1 0 -0.1 -0.2 -40 10 -15 35 60 85 differential nonlinearity vs. temperature (12 bit) max5580-85 toc10 temperature ( c) dnl (lsb) b grade midscale 2.0 1.5 1.0 0.5 0 0 1024 2048 3072 4095 supply current vs. digital input code (force sense) max5580-85 toc11 digital input code supply current (ma) slow mode 12 bit no load 1.0 0.75 0.50 0.25 0 0 1024 2048 3072 4095 supply current vs. digital input code (unity gain) max5580-85 toc12 digital input code supply current (ma) slow mode 12 bit no load supply current vs. supply voltage (force sense) max5580-85 toc13 supply voltage (v) supply current (ma) 4.80 4.10 3.40 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 0 2.70 5.25 fast mode slow mode i = i avdd + i dvdd av dd = dv dd no load supply current vs. supply voltage (unity gain) max5580-85 toc14 supply voltage (v) supply current (ma) 4.80 4.10 3.40 2.70 5.25 fast mode slow mode 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 i = i avdd + i dvdd av dd = dv dd no load shutdown supply current vs. supply voltage max5580-85 toc15 supply voltage (v) shutdown supply current (na) 4.80 4.10 3.40 2.70 5.25 55 60 65 70 75 80 85 90 95 100 50 unity gain force sense av dd = dv dd no load i = i avdd + i dvdd 7 5 6 3 1 4 2 0 -40 10 -15 35 60 85 offset error vs. temperature max5580-85 toc16 temperature ( c) offset error (lsb) code = 40 unity gain: 1 lsb = 1mv force sense: 1 lsb = 0.5mv b grade unity gain force sense 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -40 10 -15 35 60 85 gain error vs. temperature max5580-85 toc17 temperature ( c) gain error (lsb) unity gain force sense b grade unity gain: 1 lsb = 1mv force sense: 1 lsb = 0.5mv output voltage vs. output source/sink current max5580-85 toc18 i out (ma) output voltage (v) 10 5 0 -5 -10 0.5 1.0 1.5 2.0 2.5 0 -15 15 unity gain v ref = 4.096v midscale t ypical operating characteristics (continued) (av dd = dv dd = 5v, v ref = 4.096v, r l = 10k ? , c l = 100pf, speed mode = fast, pu = floating, t a = +25 c, unless otherwise noted.)
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 12 ______________________________________________________________________________________ major-carry transition glitch max5580-85 toc19 cs 2v/div (ac coupled) out_ 10mv/div 200ns/div settling time positive max5580-85 toc20 cs 2v/div out_ 2v/div 400ns/div full-scale transition settling time negative max5580-85 toc21 cs 2v/div out_ 2v/div 400ns/div full-scale transition 5 -25 1 100 1k 10 10k reference input bandwidth max5580-85 toc22 frequency (hz) gain (db) -20 -15 -10 -5 0 v ref = 0.1v p-p at 4.096v dc unity gain reference feedthrough at 1khz max5580-85 toc23 frequency (khz) 5.0 4.5 3.5 4.0 1.5 2.0 2.5 3.0 1.0 -110 -120 -130 -100 -90 -80 -70 -60 -50 -40 -30 -22 -142 0.5 5.5 dac-to-dac crosstalk max5580-85 toc24 200 s/div outa?utc 2v/div outd 2mv/div t ypical operating characteristics (continued) (av dd = dv dd = 5v, v ref = 4.096v, r l = 10k ? , c l = 100pf, speed mode = fast, pu = floating, t a = +25 c, unless otherwise noted.) digital feedthrough max5580-85 toc25 1 s/div sclk 2v/div out_ (ac-coupled) 5mv/div power-up glitch max5580-85 toc26 av dd 2v/div out_ 2v/div 20 s/div pu = dv dd exiting shutdown to midscale max5580-85 toc27 upio_ 2v/div out_ 2v/div 10 s/div pu = float
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 13 pin description pin max5580 max5582 max5584 max5581 max5583 max5585 tssop thin qfn tssop thin qfn name function 11 91 19 agnd analog ground 2202 20 av dd analog supply 3, 5, 17, 19 1, 3, 15, 17 n.c. no connection. not internally connected. 31 fbb feedback for dacb 424 2 outb dacb output 53 fba feedback for daca 646 4 outa daca output 7575pu power-up state select input. connect pu to dv dd to set out_ to full scale upon power-up. connect pu to dgnd to set out_ to zero scale upon power-up. float pu to set out_ to midscale upon power-up. 8686 cs active-low chip-select input 979 7 sclk serial clock input 10 8 10 8 din serial data input 11 9 11 9 upio1 user-programmable input/output 1 12 10 12 10 upio2 user-programmable input/output 2 13 11 13 11 dv dd digital supply 14 12 14 12 dgnd digital ground 15 13 15 13 dsp clock enable. connect dsp to dv dd to clock in data on the rising edge of sclk. connect dsp to dgnd to clock in data on the falling edge of sclk. 16 14 16 14 outd dacd output 17 15 fbd feedback for dacd 18 16 18 16 outc dacc output 19 17 fbc feedback for dacc 20 18 20 18 ref reference input ep ep ep ep exposed pad exposed pad. connect to agnd.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 14 ______________________________________________________________________________________ functional diagrams max5580 max5582 max5584 dout register 16-bit shift register cs sclk din dsp serial interface control mux av dd upio1 upio2 ref pu upio1 and upio2 logic power-down logic and register decode control input register a dac register a daca outa input register d dacd outd dac register d dv dd agnd dgnd
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 15 functional diagrams (continued) max5581 max5583 max5585 dout register 16-bit shift register cs sclk din dsp serial interface control mux av dd upio1 upio2 ref pu upio1 and upio2 logic power-down logic and register decode control input register a dac register a daca outa fba fbd input register d dacd outd dac register d dv dd agnd dgnd
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 16 ______________________________________________________________________________________ detailed description the max5580?ax5585 quad, 12-/10-/8-bit, voltage- output dacs offer buffered outputs and a 3s maximum settling time at the 12-bit level. the dacs operate from a single 2.7v to 5.25v analog supply and a separate 1.8v to av dd digital supply. the max5580?ax5585 include an input register and dac register for each channel and a 16-bit data-in/data-out shift register. the 3-wire serial interface is compatible with spi, qspi, microwire, and dsp applications. the max5580?ax5585 provide two user-programmable digital i/o ports, which are pro- grammed through the serial interface. the externally selectable power-up states of the dac outputs are either zero scale, midscale, or full scale. reference input the reference input, ref, accepts both ac and dc val- ues with a voltage range extending from analog ground (agnd) to av dd . the voltage at ref sets the full-scale output of the dacs. determine the output voltage using the following equations: unity-gain versions: v out_ = (v ref x code) / 2 n force-sense versions (fb_ connected to out_): v out = 0.5 x (v ref x code) / 2 n where code is the numeric value of the dac? binary input code and n is the bits of resolution. for the max5580/max5581, n = 12 and code ranges from 0 to 4095. for the max5582/max5583, n = 10 and code ranges from 0 to 1023. for the max5584/ max5585, n = 8 and code ranges from 0 to 255. use the minature max6126 low-dropout, ultra-low-noise ref- erence for optimum performance. output buffers the daca?acd output-buffer amplifiers of the max5580?ax5585 are unity-gain stable with rail-to- rail output voltage swings and a typical slew rate of 3.6v/? (fast mode). the max5580/max5582/ max5584 provide unity-gain outputs, while the max5581/max5583/max5585 provide force-sense out- puts. for the max5581/max5583/max5585, access to the output amplifier? inverting input provides flexibility in output gain setting and signal conditioning (see the applications information section). the max5580?ax5585 offer fast and slow settling- time modes. in the slow mode, the settling time is 6? (max), and the supply current is 1.6ma (max). in the fast mode, the settling time is 3s (max), and the sup- ply current is 4ma (max). see the digital interface section for settling-time mode programming details. use the serial interface to set the shutdown output impedance of the amplifiers to 1k ? or 100k ? for the max5580/max5582/max5584 and 1k ? or high imped- ance for the max5581/max5583/max5585. the dac outputs can drive a 10k ? (typ) load and are stable with up to 500pf (typ) of capacitive load. power-on reset at power-up, all dac outputs power up to full scale, midscale, or zero scale, depending on the configuration of the pu input. connect pu to dv dd to set out_ to full scale upon power-up. connect pu to digital ground (dgnd) at power-up to set out_ to zero scale. leave pu floating to set out_ to midscale. digital interface the max5580?ax5585 use a 3-wire serial interface that is compatible with spi, qspi, microwire, and dsp protocol applications (figures 1 and 2). connect dsp to dv dd before power-up to clock data in on the rising edge of sclk. connect dsp to dgnd before power-up to clock data in on the falling edge of sclk. after power- up, the device enters dsp frame-sync mode on the first rising edge of dsp . refer to the max5580?ax5585 programmer? handbook for details. the max5580?ax5585 include a 16-bit input shift register. the data is loaded into the input shift register through the serial interface. the 16 bits can be sent in two serial 8-bit packets or one 16-bit word ( cs must remain low until all 16 bits are transferred). the data is loaded msb first. for the max5580/max5581, the 16 bits consist of 4 control bits (c3?0) and 12 data bits (d11?0) (see table 1). for the 10-bit max5582/ max5583 devices, d11?2 are the data bits and d1 and d0 are sub-bits. for the 8-bit max5584/ max5585 devices, d11?4 are the data bits and d3?0 are sub-bits. set all sub-bits to zero for optimum performance. each dac channel includes two registers: an input reg- ister and the dac register. at power-up, the dac out- put is set according to the state of pu. the dacs are double-buffered, which allows any of the following for each channel: loading the input register without updating the dac register loading and updating the dac register without updating the input register updating the dac register from the input register updating the input and dac registers simultaneously rail-to-rail is a registered trademark of nippon motorola, ltd.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 17 table 1. serial write data format msb 16 bits of serial data lsb control bits data bits c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 figure 1. serial-interface timing diagram (dsp mode disabled) figure 2. serial-interface timing diagram (dsp mode enabled) sclk din cs doutdc1* doutdc0 or doutrb* *upio1/upio2 configured as doutdc_ (daisy-chain data output, mode 0 or 1) or doutrb (read-back data output). see the data output (doutrb, doutdc0, doutdc1) section for details. t ch t ds t cs0 t dh t csh t do1 t do2 t cl t csw t cs1 dout valid dout valid t css c1 d0 c2 c3 sclk din cs dsp doutdc0* doutdc1 or doutrb* *upio1/upio2 configured as doutdc_ (daisy-chain data output, mode 0 or 1) or doutrb (read-back data output). see the data output (doutrb, doutdc0, doutdc1) section for details. t cl t ds t ccs t dsw t dspwl t d02 t d01 t dh t cs0 t ch c3 c2 c1 d0 t csh t csw t dss t cs1 t ds0 dout valid dout valid
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 18 ______________________________________________________________________________________ sclk din c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 din sclk dv dd command takes effect here only if sclk count = n ? 16 command takes effect here only if sclk count = n ? 16 microwire or spi (cpol = 0, cpha = 0) 8-bit control data or 12-bit dac data write: cs must remain low between bytes on a 16-bit write operation spi (cpol = 1, cpha = 1) 8-bit control data or 12-bit dac data write: cs must remain low between bytes on a 16-bit write operation din sclk cs cs max5580 max5585 v dd v dd microwire sk so i/o sclk din dv dd max5580 max5585 v dd v dd spi or qspi sck mosi ss or i/o cs dsp dsp cs c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sclk din c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 din sclk dgnd command takes effect here only if sclk count = n ? 16 command takes effect here only if sclk count = n ? 16 dsp or spi (cpol = 0, cpha = 0) 8-bit control data or 12-bit dac data write: dsp or spi (cpol = 1, cpha = 0) 8-bit control data or 12-bit dac data write: din sclk cs cs max5580 max5585 v ss dsp tclk, sclk, or clkx dt or dx tfs or fsx sclk din dgnd max5580 max5585 v ss spi or qspi sck mosi ss or i/o cs dsp dsp cs cs must remain low between bytes on a 16-bit write operation cs must remain low between bytes on a 16-bit write operation figure 3. microwire and spi single dac writes (cpol = 0, cpha = 0 or cpol = 1, cpha = 1) figure 4. dsp and spi single dac writes (cpol = 0, cpha = 1 or cpol = 1, cpha = 0) serial-interface programming commands tables 2a, 2b, and 2c provide all the serial-interface programming commands for the max5580?ax5585. table 2a shows the basic dac programming com- mands, table 2b gives the advanced-feature program- ming commands, and table 2c provides the 24-bit read commands. figures 3 and 4 provide serial-inter- face diagrams for write operations. loading input and dac registers the max5580?ax5585 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit dac register for each channel (see the functional diagrams ). tables 3, 4, and 5 highlight a few of the commands that handle the loading of the input and dac registers. see table 2a for all dac programming commands.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 19 control bits data bits data c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function input registers (a?) din 0 000 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load daca input register from shift register; daca output register is unchanged; daca output is unchanged.* din 0 001 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load daca output register from shift register; input register is unchanged; daca output is updated.* din 0 010 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load daca input register and output register from shift register; daca output is updated.* din 0 011 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacb input register from shift register; dacb output register is unchanged; dacb output is unchanged.* din 0 100 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacb output register from shift register; input register is unchanged. dacb output is updated.* din 0 101 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacb input register and output register from shift register; dacb output is updated.* din 0 110 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacc input register from shift register; dacc output register is unchanged; dacc output is unchanged.* din 0 111 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacc output register from shift register; input register is unchanged; dacc output is updated.* din 1 000 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacc input register and output register from shift register; dacc output is updated.* din 1 001 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacd input register from shift register; dacd output register is unchanged; dacd output is unchanged.* din 1 010 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacd output register from shift register; input register is unchanged; dacd output is updated.* table 2a. dac programming commands
control bits data bits data c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function input registers (a?) din 1 011 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load dacd input register and output register from shift register; dacd output is updated.* din 1 100 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load all dac input registers from the shift register; all dac output registers are unchanged; all dac outputs are unchanged.* din 1 101 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 load all dac input and output registers from shift register; dac outputs are updated.* max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 20 ______________________________________________________________________________________ control bits data bits data c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function select bits din 11 100 0x xxxxx md mc mb ma load dac_ output register from input register when m_ is one; dac_ output register is unchanged if m_ is zero. shutdown-mode bits din 1 1 1 0 0 1 0 x pdd1 pdd0 pdc1 pdc0 pdb1 pdb0 pda1 pda0 write dac_ shutdown- mode bits; see table 8. din 11 100 11 xxxxxxx x x doutr xx xxx x xx pdd1 pdd0 pdc1 pdc0 pdb1 pdb0 pda1 pda0 read dac_ shutdown- mode bits. upio configuration bits din 1 1 1 0 1 0 0 x upsl2 upsl1 up3 up2 up1 up0 x x write upio configuration bits; see table 18. din 11 101 01 xxxxxxx x x doutr xx xxx x xx up3-2 up2-2 up1-2 up0-2 up3-1 up2-1 up1-1 up0-1 read upio configuration bits. settling-time-mode bits din 11 101 10 xxxxx spdd spdc spdb spda write dac_ settling-time- mode bits; see table 11. table 2b. advanced-feature programming commands * for the max5582/max5583 (10-bit version), d11?2 are the significant bits and d1 and d0 are sub-bits. for the max5584/max5585 ( 8-bit version), d11?4 are the significant bits and d3?0 are sub-bits. set all sub-bits to zero during the write commands. table 2a. dac programming commands (continued)
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 21 control bits data bits data c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function din 11 101 11 xxxxxxx x x doutr xx xxx x x xxxxx spdd spdc spdb spda read dac_ settling-time- mode bits. dac cpol/cpha bits din 1 1 1 1 0 0 0 0 x x x x x x cpol cpha write cpol, cpha control bits. din 1 1 1 1 0 0 0 1 x x x x x x x x doutr xx xxx x x xxxxxxx cpol cpha read cpol, cpha control bits. upio_ as gpi (general-purpose input) din 11 110 01 xxxxxxx x x doutrb xx xxx x x xxx rtp2 lf2 lr2 rtp1 lf1 lr1 read upio_ inputs (valid only when upio1 or upio2 is configured as a general-purpose input); see table 21. other commands din 1 1 1 1 1 1 0 0 x x x x x x x x command is ignored. din 1 1 1 1 1 1 0 1 x x x x x x x x command is ignored. din 1 1 1 1 1 1 1 0 x x x x x x x x command is ignored. din 1111111111111111 16-bit no-op command. all dacs are unaffected. table 2b. advanced-feature programming commands (continued) x = don? care.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 22 ______________________________________________________________________________________ control bits data bits data c3 c2 c1 c0 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function read input and dac registers a? din 1111010x1111111111111111 xxxxxxxx doutrb xxxxxxxx d23 d22 d21 d20 d19 d18 d17 d16 d15/x d14/x d13/x d12/x d11 d10 d9 d8 d7 d6 d5 d4 d3/x d2/x d1/x d0/x read input register a and dac register a (all 24 bits).** ? din 1111011x1111111111111111 xxxxxxxx doutrb xxxxxxxx d23 d22 d21 d20 d19 d18 d17 d16 d15/x d14/x d13/x d12/x d11 d10 d9 d8 d7 d6 d5 d4 d3/x d2/x d1/x d0/x read input register b and dac register b (all 24 bits).** ? din 1111100x1111111111111111 xxxxxxxx doutrb xxxxxxxx d23 d22 d21 d20 d19 d18 d17 d16 d15/x d14/x d13/x e12/x d11 d10 d9 d8 d7 d6 d5 d4 d3/x d2/x d1/x d0/x read input register c and dac register c (all 24 bits).** ? din 1111101x1111111111111111 xxxxxxxx doutrb xxxxxxxx d23 d22 d21 d20 d19 d18 d17 d16 d15/x d14/x d13/x e12/x d11 d10 d9 d8 d7 d6 d5 d4 d3/x d2/x d1/x d0/x read input register d and dac register d (all 24 bits).** ? table 2c. 24-bit read commands x = don? care. ** d23?12 represent the 12-bit data from the appropriate dac output register. d11?0 represent the 12-bit data from the correspon ding input register. for the max5582/max5583, bits d13, d12, d1, and d0 are don?-care bits. for the max5584/max5585, bits d15?12 and d3?0 are don ?-care bits. ? during readback, all ones (0xff) must be clocked into din for all 24 bits. no command can be issued before all 24 bits have bee n clocked out. cs must be kept low while all 24 bits are clocked out.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 23 dac programming examples: to load input register a from the shift register, leaving dac register a unchanged (dac output unchanged), use the command in table 3. the max5580?ax5585 can load all the input registers (a?) simultaneously from the shift register, leaving the dac registers unchanged (dac output unchanged), by using the command in table 4. to load all the input registers (a?) and all the dac regis- ters (a?) simultaneously, use the command in table 5. for the 10-bit and 8-bit versions, set sub-bits = 0 for best performance. advanced-feature programming commands select bits (m_) the select bits allow synchronous updating of any com- bination of channels. the select bits command the loading of the dac register from the input register of each channel. set the select bit m_ = 1 to load the dac register ??with data from the input register ?? where ??is replaced with a, b, c, or d, depending on the selected channel. setting the select bit m_ = 0 results in no action for that channel (table 6). select bits programming example: to load dac register b from input register b while keeping other channels (a, c, d) unchanged, set mb = 1 and m_ = 0 (table 7). table 3. load input register a from shift register table 4. load input registers (a?d) from shift register table 5. load input registers (a?d) and dac registers (a?d) from shift register table 6. select bits (m_) data control bits data bits din 0000 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 1 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 1 1 0 1 d11 d10 d9 d8 d7 d6 d5 d4 d3/0 d2/0 d1/0 d0/0 data control bits data bits din 1 1 1000xxxxxxmdmcmbma table 7. select bits programming example data control bits data bits din 111 000xxxxxx0010 x = don? care. x = don? care.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 24 ______________________________________________________________________________________ table 9. shutdown-mode write command table 10. shutdown-mode-bits write example data control bits data bits din 1110010x p d d 1p d d 0p d c 1p d c 0p d b1 p d b0 p d a1 p d a0 data control bits data bits din 1110010x01010100 x = don? care. table 11. settling-time-mode write command data control bits data bits din 1110110xx x x x s p d d s p d c s p d b s p d a x = don? care. shutdown-mode bits (pd_0, pd_1) use the shutdown-mode bits and control bits to shut down each dac independently. the shutdown- mode bits determine the output state of the selected channels. the shutdown-control bits put the selected channels into shutdown mode. to select the shutdown mode for daca?acd, set pd_0 and pd_1 according to table 8 (where ??is replaced with one of the select- ed channels (a?)). the three possible states for unity- gain versions are 1) normal operation, 2) shutdown with 1k ? output impedance, and 3) shutdown with 100k ? output impedance. the three possible states for force- sense versions are 1) normal operation, 2) shutdown with 1k ? output impedance, and 3) shutdown with the output in a high-impedance state. table 9 shows the com- mands for writing to the shutdown-mode bits. table 10 shows an example of writing the shutdown-control bits. this command shuts down daca with 1k ? to ground and shuts down dacb?acd with 100k ? to ground. always write the shutdown-mode-bits command first and then write the shutdown-control-bits command to proper- ly shut down the selected channels. the shutdown- control-bits command can be written at any time after the shutdown-mode-bits command. it does not have to immediately follow the shutdown-mode-bits command. settling-time-mode bits (spd_) the settling-time-mode bits select the settling time (fast mode or slow mode) of the max5580?ax5585. set spd_ = 1 to select fast mode or set spd_ = 0 to select slow mode, where ??is replaced by a, b, c, or d, depending on the selected channel (table 11). fast mode provides a 3? maximum settling time, and slow mode provides a 6? maximum settling time. table 8. shutdown-mode bits pd_1 pd_0 description 00 shutdown with 1k ? termination to ground on dac_ output. 01 shutdown with 100k ? termination to ground on dac_ output for unity-gain versions. shutdown with high-impedance output for force-sense versions. 10 ignored. 11 dac_ is powered up in its normal operating mode. x = don? care.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 25 settling-time-mode write example: to configure daca and dacd into fast mode and dacb and dacc into slow mode, use the command in table 12. to read back the settling-time-mode bits, use the com- mand in table 13. cpol and cpha control bits the cpol and cpha control bits of the max5580?ax5585 are defined the same as the cpol and cpha bits in the spi standard. set the dac? cpol and cpha bits to cpol = 0 and cpha = 0 or cpol = 1 and cpha = 1 for microwire and spi applications requiring the clocking of data in on the ris- ing edge of sclk. set the dac? cpol and cpha bits to cpol = 0 and cpha = 1 or cpol = 1 and cpha = 0 for dsp and spi applications, requiring the clocking of data in on the falling edge of sclk (refer to the programmer? handbook and see table 14 for details). at power-up, if dsp = dv dd , the default value of cpha is zero and if dsp = dgnd, the default value of cpha is one. the default value of cpol is zero at power-up. to write to the cpol and cpha bits, use the command in table 15. to read back the device? cpol and cpha bits, use the command in table 16. table 12. settling-time-mode write example data control bits data bits din 1110110xxxxx1001 x = don? care. table 13. settling-time-mode read command data control bits data bits din 1 1 1 01111xx xxxxxx d ou trb xxxxxx xxx x x x s p d d s p d c s p d b s p d a table 16. cpol and cpha read command data control bits data bits din 1 1 1 1 0 0 0 1 x x x x x x x x d ou trb xxx xxxxx xxxxxx c p o l c p h a table 14. cpol and cpha bits cpol cpha description 00 default values at power-up when dsp is connected to dv dd . data is clocked in on the rising edge of sclk. 01 default values at power-up when dsp is connected to dgnd. data is clocked in on the falling edge of sclk. 10 data is clocked in on the falling edge of sclk. 11 data is clocked in on the rising edge of sclk. table 15. cpol and cpha write command data control bits data bits din 11110000xxxxxx c p o l c p h a x = don? care. x = don? care. x = don? care.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 26 ______________________________________________________________________________________ table 19. upio programming example data control bits data bits din 1110100x010000xx x = don? care. table 20. upio read command data control bits data bits din 1110101 xxxxxxxxx doutrb xxxxxxxx u p 3- 2u p 2- 2u p 1- 2u p 0- 2u p 3- 1u p 2- 1u p 1- 1 u p 0- 1 x = don? care. upio bits (upsl1, upsl2, up0?p3) the max5580?ax5585 provide two user-programma- ble input/output (upio) ports: upio1 and upio2. these ports have 15 possible configurations, as shown in table 21. upio1 and upio2 can be programmed inde- pendently or simultaneously by writing to the upsl1, upsl2, and up0?p3 bits (table 17). table 18 shows how upio1 and upio2 are selected for configuration. the up0?p3 bits select the desired functions for upio1 and/or upio2 (table 21). upio programming example: to set only upio1 as ldac and leave upio2 unchanged, use the command in table 19. the upio selection and configuration bits can be read back from the max5580?ax5585 when upio1 or upio2 is configured as a doutrb output. table 20 shows the read-back data format for the upio bits. writing the command in table 20 initiates a read opera- tion of the upio bits. the data is clocked out starting on the 9th clock cycle of the sequence. bits up3-2 through up0-2 provide the up3?p0 configuration bits for upio2 (table 21), and bits up3-1 through up0-1 pro- vide the up3?p0 configuration bits for upio1. table 17. upio write command data control bits data bits din 1110100x u p s l2 u p s l1 up3 up2 up1 up0 xx x = don? care. table 18. upio selection bits (upsl1 and upsl2) upsl2 upsl1 upio port selected 00 none selected 01 upio1 selected 10 upio2 selected 11 both upio1 and upio2 selected
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 27 upio configuration table 21 lists the possible configurations for upio1 and upio2. upio1 and upio2 use the selected function when configured by the up3?p0 configuration bits. ldac ldac controls the loading of the dac registers. when ldac is high, the dac registers are latched, and any change in the input registers does not affect the con- tents of the dac registers or the dac outputs. when ldac is low, the dac registers are transparent, and the values stored in the input registers are fed directly to the dac registers, and the dac outputs are updated. drive ldac low to asynchronously load the dac regis- ters from their corresponding input registers (dacs that are in shutdown remain shut down). the ldac input does not require any activity on cs , sclk, or din to take effect. if ldac is brought low coincident with a ris- ing edge of cs (which executes a serial command modifying the value of either dac input register), then ldac must remain asserted for at least 120ns following the cs rising edge. this requirement applies only for serial commands that modify the value of the dac input registers. see figures 5 and 6 for timing details. table 21. upio configuration register bits (up3?up0) upio configuration bits up3 up2 up1 up0 function description 0000 ldac active-low load dac input. drive low to asynchronously load all dac registers with data from input registers. 0001 set active-low input. drive low to set all input and dac registers to full scale. 0010 mid active-low input. drive low to set all input and dac registers to midscale. 0011 clr active-low input. drive low to set all input and dac registers to zero scale. 0100 pdl active-low power-down lockout input. drive low to disable software shutdown. 0101 reserved this mode is reserved. do not use. 0110 shdn1k active-low 1k ? shutdown input. overrides pd_1 and pd_0 settings. for the max5580/max5582/max5584, drive shdn1k low to pull outa?utd to agnd with 1k ? . for the max5581/max5583/max5585, drive shdn1k low to leave outa?utd high impedance. 0111 shdn100k active-low 100k ? shutdown input. overrides pd_1 and pd_0 settings. for the max5580/max5582/max5584, drive shdn100k low to pull outa?utd to agnd with 100k ? . for the max5581/max5583/max5585, drive low to leave outa?utd high impedance. 1000 doutrb data read-back output 1001 doutdc0 m od e 0 d ai sy- c hai n d ata o utp ut. d ata i s cl ocked out on the fal l i ng ed g e of s c lk. 1010 doutdc1 mode 1 daisy-chain data output. data is clocked out on the rising edge of sclk. 1011 gpi general-purpose logic input 1100 gpol general-purpose logic-low output 1101 gpoh general-purpose logic-high output 1110 togg toggle input. toggles dac outputs between data in input registers and data in dac registers. drive low to set all dac outputs to values stored in input registers. drive high to set all dac outputs to values stored in dac registers. 1111 fast fast/slow settling-time-mode input. drive low to select fast (3?) mode or drive high to select slow (6?) settling mode. overrides the spda?pdd settings.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 28 ______________________________________________________________________________________ set , mid , clr the set , mid , and clr signals force the dac outputs to full scale, midscale, or zero scale (figure 5). these signals cannot be active at the same time. the active-low set input forces the dac outputs to full scale when set is low. when set is high, the dac out- puts follow the data in the dac registers. the active-low mid input forces the dac outputs to midscale when mid is low. when mid is high, the dac outputs follow the data in the dac registers. the active-low clr input forces the dac outputs to zero scale when clr is low. when clr is high, the dac outputs follow the data in the dac registers. if clr , mid , or set signals go low during a write com- mand, reload the data to ensure accurate results. power-down lockout ( pdl ) the pdl active-low, software-shutdown lockout input overrides (not overwrites) the pd_0 and pd_1 shutdown- mode bits. pdl cannot be active at the same time as shdn1k or shdn100k (see the shutdown mode ( shdn1k , shdn100k ) section). if the pd_0 and pd_1 bits command the dac to shut down prior to pdl going low, the dac returns to shutdown mode immediately after pdl goes high, unless the pd_0 and pd_1 bits were modified through the serial interface in the meantime. shutdown mode ( s s h h d d n n 1 1 k k , s s h h d d n n 1 1 0 0 0 0 k k ) the shdn1k and shdn100k are active-low signals that override (not overwrite) the pd_1 and pd_0 bit set- tings. for the max5580/max5582/max5584, drive shdn1k low to select shutdown mode with outa outd internally terminated with 1k ? to ground, or drive shdn100k low to select shutdown with an internal 100k ? termination. for the max5581/max5583/ max5585, drive shdn1k low for shutdown with 1k ? output termination, or drive shdn100k low for shut- down with high-impedance outputs. data output (doutrb, doutdc0, doutdc1) upio1 and upio2 can be configured as serial data out- puts, doutrb (data out for read back), doutdc0 (data out for daisy-chaining, mode 0), and doutdc1 (data out for daisy-chaining, mode 1). the differences between doutrb and doutdc0 (or doutdc1) are as follows: the source of read-back data on doutrb is the dout register. daisy-chain doutdc_ data comes directly from the shift register. read-back data on doutrb is only present after a dac read command. daisy-chain data is present on doutdc_ for any dac write after the first 16 bits are written. the doutrb idle state ( cs = high) for read back is high impedance. daisy-chain doutdc_ idles high when inactive to avoid floating the data input in the next device in the daisy-chain. see figures 1 and 2 for timing details. t gp t lds end of cycle* gpo_ ldac * end-of-cycle represents the rising edge of cs or the 16th active clock edge, depending on the mode of operation. t cms t ldl t s 0.5 lsb togg v out_ ldac pdl clr, mid, or set pdl affects dac outputs (v out_ ) only if dacs were previously shut down. figure 5. asynchronous signal timing figure 6. gpo_ and ldac signal timing
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 29 gpi, gpol, gpoh upio1 and upio2 can each be configured as a gener- al-purpose input (gpi), a general-purpose output low (gpol), or a general-purpose output high (gpoh). the gpi can serve to detect interrupts from ?s or micro- controllers. the gpi has three functions: 1) sample the signal at gpi at the time of the read (rtp1 and rtp2). 2) detect whether a falling edge has occurred since the last read or reset (lf1 and lf2). 3) detect whether a rising edge has occurred since the last read or reset (lr1 and lr2). rtp1, lf1, and lr1 represent the data read from upio1; rtp2, lf2, and lr2 represent the data read from upio2. to issue a read command for the upio configured as gpi, use the command in table 22. once the command is issued, rtp1 and rtp2 provide the real-time status (0 or 1) of the inputs at upio1 or upio2, respectively, at the time of the read. if lf2 or lf1 is one, then a falling edge has occurred on the respective upio1 or upio2 input since the last read or reset. if lr2 or lr1 is one, then a rising edge has occurred since the last read or reset. gpol outputs a constant low, and gpoh outputs a constant high. see figure 6. togg use the togg input to toggle the dac outputs between the values in the input registers and dac reg- isters. a delay of greater than 100ns from the end of the previous write command is required before the togg signal can be correctly switched between the new value and the previously stored value. when togg = 0, the output follows the information in the input regis- ters. when togg = 1, the output follows the informa- tion in the dac register (figure 5). fast the max5580?ax5585 have two settling-time-mode options: fast (3? max) and slow (6? max). to select the fast mode, drive fast low, and to select slow mode, drive fast high. this overrides (not over- writes) the spda?pdd bit settings. table 22. gpi read command data control bits data bits din 1111001 xxxxxxxxx doutrb xxxxxxxxxx rtp2 lf2 lr2 rtp1 lf1 lr1 table 23. unipolar code table (gain = +1) dac contents msb lsb analog output 1111 1111 1111 +v ref (4095 / 4096) 1000 0000 0001 +v ref (2049 / 4096) 1000 0000 0000 +v ref (2048 / 4096) = v ref / 2 0111 1111 1111 +v ref (2047 / 4096) 0000 0000 0001 +v ref (1 / 4096) 0000 0000 0000 0 max5580 dac_ ref out_ v out_ = v ref_ x code / 4096 where code is the dac input code (0 to 4095 decimal) max6126 figure 7. unipolar output circuit x = don? care.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 30 ______________________________________________________________________________________ applications information unipolar output figure 7 shows the unity-gain max5580 in a unipolar output configuration. table 23 lists the unipolar out- put codes. bipolar output the max5580 outputs can be configured for bipolar operation, as shown in figure 8. the output voltage is given by the following equation: v out_ = v ref x (code - 2048) / 2048 where code represents the numeric value of the dac? binary input code (0 to 4095 decimal). table 24 shows digital codes and the corresponding output volt- age for the circuit in figure 8. configurable output gain the max5581/max5583/max5585 have force-sense outputs, which provide a direct connection to the invert- ing terminal of the output op amp, yielding the most flexibility. the force-sense output has the advantage that specific gains can be set externally for a given application. the gain error for the max5581/max5583/ max5585 is specified in a unity-gain configuration (op- amp output and inverting terminals connected), and additional gain error results from external resistor tolerances. the force-sense dacs allow many useful circuits to be created with only a few simple external components. an example of a custom, fixed gain using the max5581? force-sense output is shown in figure 9. in this example, the external reference is set to 1.25v, and the gain is set to +1.1v/v with external discrete resis- tors to provide an approximate 0 to 1.375v dac output voltage range. v out = [(0.5 x v ref_ x code) / 4096] x [1 + (r2 / r1)] where code represents the numeric value of the dac? binary input code (0 to 4095 decimal). in this example, r2 = 12k ? and r1 = 10k ? to set the gain = 1.1v/v: v out = [(0.5 x 1.25v x code) / 4096] x 2.2 table 24. bipolar code table (gain = +1) dac contents msb lsb analog output 1111 1111 1111 +v ref (2047 / 2048) 1000 0000 0001 +v ref (1 / 2048) 1000 0000 0000 0 0111 1111 1111 -v ref (1 / 2048) 0000 0000 0001 -v ref (2047 / 2048) 0000 0000 0000 -v ref (2048 / 2048) = -v ref figure 8. bipolar output circuit max5580 max5582 max5584 dac_ ref 10k ? 10k ? v+ v- v out_ max6126 max5581 dac_ ref out_ fb_ r2 = 12k ? 0.1% 25ppm r1 = 10k ? 0.1% 25ppm max6126 figure 9. configurable output gain
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 31 power-supply and layout considerations bypass the analog and digital power supplies by using a 10? capacitor in parallel with a 0.1? capacitor to agnd and dgnd (figure 10). minimize lead lengths to reduce lead inductance. use shielding and/or ferrite beads to fur- ther increase isolation. digital and ac transient signals coupling to agnd can create noise at the output. connect agnd to the high- est quality ground available. use proper grounding techniques, such as a multilayer board with a low- inductance ground plane. wire-wrapped boards and sockets are not recommended. for optimum system performance, use pc boards with separate analog and digital ground planes. connect the two ground planes together at the low-impedance power-supply source. using separate power supplies for av dd and dv dd improves noise immunity. connect agnd and dgnd at the low-impedance power-supply sources (figure 11). max5580 max5585 10 f 0.1 f dv dd av dd dv dd agnd*** dgnd*** 10 f 0.1 f av dd 1 f** 0.1 f** max6126 ref outa fba* outb fbb* outc fbc* outd fbd* upio1 upio2 sclk din pu cs dsp *max5581/max5583/max5585 only. **remove bypass capacitors on ref for an ac reference input. ***connect analog and digital ground at the planes at the low-impedance power-supply source. figure 10. bypassing power supplies av dd , dv dd , and ref max5580?ax5585 0.1 f 10 f av dd agnd av dd agnd 0.1 f 10 f dv dd dgnd dv dd dgnd dv dd dgnd analog supply digital supply digital circuitry figure 11. separate analog and digital power supplies
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs 32 ______________________________________________________________________________________ chip information transistor count: 24,393 process: bicmos top view 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 ref n.c. (*fbc) outc n.c. (*fbd) outb n.c. (*fbb) av dd agnd outd dsp dgnd dv dd cs pu outa n.c. (*fba) 12 11 9 10 upio2 upio1 din sclk max5580 max5585 tssop 20 19 18 17 av dd agnd ref n.c. (*fbc) 16 outc 13 12 11 14 15 dgnd dsp outd n.c. (*fbd) dv dd 4 3 2 1 outa n.c. (*fba) outb n.c. (*fbb) 5 pu 6789 cs sclk din upio1 10 upio2 max5580 max5585 thin qfn *for the max5581/max5583/max5585 **exposed paddle connected to agnd **ep **ep pin configurations part temp range pin-package max5580beup -40? to +85? 20 tssop-ep** max5580betp -40? to +85? 20 thin qfn-ep** max5581 aeup* -40? to +85? 20 tssop-ep** max5581aetp* -40? to +85? 20 thin qfn-ep** max5581beup -40? to +85? 20 tssop-ep** max5581betp -40? to +85? 20 thin qfn-ep** max5582 eup -40? to +85? 20 tssop-ep** max5582etp -40? to +85? 20 thin qfn-ep** max5583 eup -40? to +85? 20 tssop-ep** max5583etp -40? to +85? 20 thin qfn-ep** max5584 eup -40? to +85? 20 tssop-ep** max5584etp -40? to +85? 20 thin qfn-ep** max5585 eup -40? to +85? 20 tssop-ep** max5585etp -40? to +85? 20 thin qfn-ep** ordering information (continued) * future product?ontact factory for availability. specifications are preliminary. ** ep = exposed paddle.
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs ______________________________________________________________________________________ 33 pa ck ag e information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l e 1 2 21-0140 package outline 16, 20, 28, 32, 40l, thin qfn, 5x5x0.8mm detail b l l1 e common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 e 2 2 21-0140 package outline 16, 20, 28, 32, 40l, thin qfn, 5x5x0.8mm l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. - 40 10 10 5.00 5.00 0.20 0.50 0.40 bsc. 0.40 0.25 4.90 4.90 0.15 0.60 5.10 5.10 0.25 40l 5x5 0.20 ref. 0.75 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 - 0.35 0.45 0.30 0.40 0.50 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 3.40 3.20 3.30 t4055-1 3.20 3.30 3.40 no no no no no no no no yes yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes
max5580?ax5585 buffered, fast-settling, quad, 12-/10-/8-bit, voltage-output dacs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 34 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. pa ck ag e information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) tssop 4.4mm body.eps d 1 1 21-0108 package outline, tssop, 4.40 mm body exposed pad

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